1. Field of the Invention
The present invention relates to a method of forming conductor lines of a semiconductor device, and more particularly, to a method of electroplating a gold (Au) layer on an underlying conductive layer for the conductor lines.
As a step toward the miniaturization thereof, a semiconductor integrated circuit device is provided with fine patterned conductor lines, but to enable a relatively large electric current to be passed through these conductor lines, they should be made thicker.
2. Description of the Related Art
To form conductor lines being relatively thick, an electroplating technique of gold has been adopted as shown, for example, in FIGS. 1A to 1E illustrating a formation of the gold conductor lines.
As shown in FIG. 1A, in accordance with a conventional producing technique, a SiO.sub.2 layer 2 is formed on a Si substrate 1, Al conductor lines 3 are formed on the SiO.sub.2 layer 2, and then an insulating (e.g., PSG) layer 4 is formed thereover. Contact holes 5 are formed in the insulating layer 4 by a conventional lithography process, and a double-layer barrier metal (conductive) layer 6 composed of a titanium (Ti) layer and a palladium (Pd) layer is formed over the insulating layer 4 and the Al conductor layer 3 exposed within the contact holes 5. Thereafter, a photo-sensitive resin is deposited on the barrier metal layer 6 by a spin-coating method, to form a resist layer 7.
As shown in FIG. 1B, the resist layer 7 is selectively exposed by a light, an electron beam or the like, and then developed to form openings 8 having the same shape as the conductor lines 3 and covering the contact holes 5. Namely, the resist layer 7 is suitably patterned.
Then, as shown in FIG. 1C, gold is deposited on the barrier layer 6 within the openings 8, in a gold plating bath by an electroplating technique, to form a gold layer 9a, 9b having a thickness of, e.g., 5 .mu.m. The barrier layer 6 is connected to a cathode terminal of an electric power source to serve as a cathode electrode and an anode electrode of, e.g., platinum or the like is connected to an anode terminal of the power source.
As shown in FIG. 1D, the patterned resist layer 7 is then removed, and using the gold plated layer 9a and 9b as a mask, the barrier (Ti/Pd) layer 6 is selectively etched by a suitable wet-etching process to finally form conductor lines 10 composed of the gold plated layer 9a, 9b and the patterned barrier layer 6.
At a next step of a production of a semiconductor device, as shown in FIG. 1E, a protective (passivation) insulating layer 11 is formed over the whole surface of the conductor lines 10 and the insulating layer 4. The protective layer 11 is usually made of an insulating material such as PSG, Si.sub.3 N.sub.4, is deposited by a chemical vapor deposition (CVD) process, a sputtering process or the like, and has a thickness of from 1 to 2 .mu.m.
As can be seen in FIG. 1E, the gold plated layer 9a, 9b has sharp edges at the almost right angle corners thereof, and there is a large step between the top surface of the conductor lines 10 and the surface of the insulating layer 4, having a height of, e.g., about 6 .mu.m, as shown in FIG. 1D. Accordingly, when the protective layer 11 is formed, these sharp edges and the large step adversely affect the step coverage of the formed layer 11. For example, the thickness of the protective layer 11 is reduced at the sharp edges, as shown in FIG. 1E; in the worst state, the protective layer 11 is separated by the sharp edges, and thus the conductor lines 10 are not fully covered. Furthermore, the sharp edges increase the stress concentration, which will cause the appearance of cracks 12. If the distance between the adjacent conductor lines 10 is narrow, as shown in FIG. 2, the protective layer 11 may form a porosity (pipe) 13 because the top portions thereof are extended toward the center of the gap between the conductor lines 10 and joined together at that point. In this case, when a rise of an ambient temperature occurs, the gas in the porosity 13 is expands and causes cracks 14 to appear in the protective layer 11 surrounding the porosity 13. Such an adverse step coverage and the appearance of cracks lowers the reliability of the semiconductor device.